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altera corporation 969 understanding max 5000 & classic timing may 1999, ver. 3 application note 78 a-an-078-03 introduction altera ? devices provide performance that is consistent from simulation to application. before programming a device, you can determine the worst- case timing delays for any design. you can calculate propagation delays either with the max+plus ? ii timing analyzer or with the timing models given in this application note and the timing parameters listed in individual device data sheets. both methods yield the same results. this application note defines internal and external timing parameters, and illustrates the timing models for the max ? 5000 (including max 5000a), and classic ? device families. familiarity with device architecture and characteristics is assumed. refer to the device family data sheets in this data book for complete descriptions of the architectures, and for the specific values of the timing parameters listed in this application note. internal timing parameters within a device, the timing delays contributed by individual architectural elements are called internal timing parameters, which cannot be measured explicitly. all internal timing parameters are shown in italic type. the following section defines the internal timing parameters for max 5000 and classic devices, and applies to both device families unless otherwise indicated. classic devices include the ep610, ep610i, ep910, ep910i , and ep1810 devices only. t in the time required for a dedicated input pin to drive the true and complement data input signal into the logic array(s). t io i/o input pad and buffer delay. the t io delay applies to i/o pins used as inputs. in multi-lab max 5000 devices, t io is the delay from the i/o pin to the pia. in max 5000 devices with a single logic array block (lab), t io is the delay from the i/o pin to the logic arrays. in classic devices, t io is the delay added to t in . t pia programmable interconnect array (pia) delay. the delay incurred by signals that require routing through the pia. multi-lab max 5000 devices only.
970 altera corporation an 78: under standing max 5000 & classic timing t sexp shar ed expander array delay . the delay of a signal thr ough the and-not str uctur e of the shar ed expander pr oduct-term array that is fed back into the logic array . max 5000 devices only . t ics global clock delay . the delay fr om the dedicated clock pin to a r egister s clock input. t lac logic array contr ol delay . the and array delay for r egister contr ol functions such as pr eset, clear , and output enable. max 5000 devices only . t ic array clock delay . the delay thr ough a macr ocells clock pr oduct term to the r egister s clock input. t clr register clear time. the delay fr om the assertion of the r egister s asynchr onous clear input to the time the r egister output stabilizes at logical low . t pre register pr eset time. the delay fr om the assertion of the r egister s asynchr onous pr eset input to the time the r egister output stabilizes at logical high. t lad logic array delay . the time a logic signal r equir es to pr opagate thr ough a macr ocells and-or-xor str uctur e. t rd register delay . the delay fr om the rising edge of the r egister s clock to the time the data appears at the r egister output. max 5000 devices only . t comb combinatorial buf fer delay . the delay fr om the time when a combinatorial logic signal bypasses the pr ogrammable r egister to the time it becomes available at the macr ocell output. max 5000 devices only . t la tch latch delay . the pr opagation delay thr ough the pr ogrammable r egister when t la tch is con? gur ed as a ? ow-thr ough latch. max 5000 devices only . t su register setup time. the time r equir ed for a signal to be stable at the r egister input befor e the r egister clocks rising edge to ensur e that the r egister corr ectly stor es the input data. t h register hold time. the time r equir ed for a signal to be stable at the r egister input after the r egister clocks rising edge to ensur e that the r egister corr ectly stor es the input data.
altera corporation 971 an 78: under standing max 5000 & classic timing t fd feedback delay . in single-lab max 5000 devices, t fd is the delay of a macr ocell output fed back into the logic array . in multi-lab max 5000 devices, t fd is the delay of a macr ocell output fed back into the labs logic array or to a pia input. in classic devices, t fd is the delay of a macr ocell output fed back into the logic array . t od output buf fer and pad delay . t xz output buf fer disable delay . the delay r equir ed for high impedance to appear at the output pin after the output buf fer s enable contr ol is disabled. t zx output buf fer enable delay . the delay r equir ed for the output signal to appear at the output pin after the tri-state buf fer s enable contr ol is enabled. exte rnal t iming parameters external timing parameters represent actual pin-to-pin timing characteristics. each external timing parameter consists of a combination of internal timing parameters. the data sheet for each device gives the values of the external timing parameters. these external timing parameters are worst-case values, derived from extensive performance measurements and ensured by testing. all external timing parameters are shown in bold type. the following list defines external timing parameters for max 5000 and classic devices. classic devices include the ep610, ep610i, ep910, ep910i , and ep1810 devices only. t pd1 dedicated input pin to non-r egister ed output delay . the time r equir ed for a signal on any dedicated input pin to pr opagate thr ough the combinatorial logic in a macr ocell and appear at an external device output pin. t pd2 i/o pin input to non-r egister ed output delay . the time r equir ed for a signal on any i/o pin input to pr opagate thr ough the combinatorial logic in a macr ocell and appear at an external device output pin. t pzx t ri-state to active output delay . the time r equir ed for an input transition to change an external output fr om a tri-state (high- impedance) logic level to a valid high or low logic level. t pxz active output to tri-state delay . the time r equir ed for an input transition to change an external output fr om a valid high or low logic level to a tri-state (high-impedance) logic level. t clr t ime to clear r egister delay . the time r equir ed for a low signal to appear at the external output, measur ed fr om the input transition.
972 altera corporation an 78: under standing max 5000 & classic timing t su global clock setup time. the time that data must be pr esent at the input pin befor e the global (synchr onous) clock signal is asserted at the clock pin. t h global clock hold time. the time that data must be pr esent at the input pin after the global clock signal is asserted at the clock pin. t co1 global clock to output delay . the time r equir ed to obtain a valid output after the global clock is asserted at the clock pin. t cnt minimum global clock period. the minimum period maintained by a globally clocked counter . t asu array clock setup time. the time data must be pr esent at an input pin befor e an array (asynchr onous) clock signal is asserted at the input pin. t ah array clock hold time. the time data must be pr esent at an input pin after an array clock signal is asserted at the input pin. t aco1 array clock to output delay . the time r equir ed to obtain a valid output after an array clock signal is asserted at an input pin. t acnt minimum array clock period. the minimum period maintained by a counter when it is clocked by a signal fr om the array . t iming models timing models are simplified block diagrams that illustrate the propagation delays through altera devices. logic can be implemented on different paths. you can trace the actual paths used in your design by examining the equations listed in the max+plus ii report file ( .rpt ) for the project. you can then add up the appropriate internal timing parameters to calculate the propagation delays through the device. max 5000 devices the max 5000 architecture supports many functions. the macrocell array provides registered, combinatorial, or flow-through latch operation. the registers can be clocked from a global clock or through product-term array clocks, and can be asynchronously preset and cleared. separate product terms control the output enable and logic inversion signals. the array of shared expander product terms provides additional product terms to implement complex logic. the max 5000 family has single- and multi-lab devices. figure 1 shows the timing model for the single-lab epm5032 device.
altera corporation 973 an 78: under standing max 5000 & classic timing figure 1. single-lab max 5000 device t iming model figure 2 sh ows the timing model for the multi-lab max 5000 devices: the epm5064, epm5128, epm5130, and epm5192 devices. in multi-lab devices, the pia routes signals between different labs. all i/o inputs enter the logic array through the pia. signals routed through the pia incur an additional delay. figure 2. multi-lab max 5000 device t iming model i/o dela y t io logic arra y dela y t lad input dela y t in logic arra y control dela y t la c f eedback dela y t fd output delay t od t xz t zx register delay t rd t comb t la tch t clr t pre t su t h shared expander dela y t sexp array clock delay t ic global clock delay t ics pia dela y t pia logic arr a y dela y t lad input dela y t in logic arr a y control dela y t la c f eedbac k dela y t fd output delay t od t xz t zx register delay t rd t comb t la tch t clr t pre t su t h shared expander dela y t sexp array cloc k delay t ic global cloc k delay t ics i/o dela y t io
974 altera corporation an 78: under standing max 5000 & classic timing classic devices the architecture for the classic device family, which includes the ep610, ep610i, ep910, ep910i , and ep1810 devices, provides registered and combinatorial capabilities. registers can be clocked from a global clock or through a product-term array clock, and can be asynchronously cleared. when the global clock is used, the output enable signal can be controlled by a product term. figure 3 shows the timing model for these classic devices. figure 3. classic device t iming model if the register is bypassed, the delay between the logic array and the output buffer is zero. calculating t iming delays you can calculate pin-to-pin timing delays for any device with the appropriate timing model and internal timing parameters. each external timing parameter is calculated from a combination of internal timing parameters. figure 4 shows the external timing parameters for the max 5000 and classic device families. classic devices include the ep610, ep610i, ep910, ep910i , and ep1810 devices only. to calculate the delay for a signal that follows a different path through the device, refer to the timing models shown in figures 1 through 3 to determine which internal timing parameters to add together. register t su t h i/o delay t io feedback delay t fd input delay t i n logic array delay t lad t clr array clock delay t ic output delay t od t xz t zx global clock delay t ics
altera corporation 975 an 78: under standing max 5000 & classic timing figure 4. external t iming parameters (part 1 of 3) combinatorial logic combinatorial delay combinatorial logic t ri-state enable/disable delay register clear & preset t ime max 5000 clr t pre , t clr = t in + t lac + ( t pre or t ) + t od t clr = t in + t clr + t od classic max 5000 (multi-lab) max 5000 (single-lab) pd2 io lad comb od classic max 5000 classic zx t pxz , t pzx = t in + t lad + ( t xz or t ) zx t pxz , t pzx = t in + t lac + ( t xz or t ) pd2 io in lad od t pd1 = t in + t lad + t od t = t + t + t + t t = t + t + t + t pd1 in lad comb od t pd1 = t in + t lad + t comb + t od t = t + t + t + t pd2 io pia lad comb od t = t + t + t + t + t combinatorial logic
976 altera corporation an 78: under standing max 5000 & classic timing figure 4. external timing parameters (part 2 of 3) combinatorial logic setup t ime combinatorial logic counter frequency max 5000 combinatorial logic combinatorial logic asynchronous setup t ime max 5000 max 5000 max 5000 combinatorial logic hold t ime lad ics t su = ( t in + t ) C ( t in + t ) + t su lad ics t su = ( t in + t ) C ( t in + t ) + t su in ics in lad h ics lad t h = ( t in + t ) C ( t in + t ) + t h cnt rd fd lad su t = t + t + t + t t cnt = t fd + t lad + t su lad ic t asu = ( t in + t ) C ( t in + t ) + t su lad ic t asu = ( t in + t ) C ( t in + t ) + t su classic classic classic h t = ( t + t ) C ( t + t ) + t classic
altera corporation 977 an 78: under standing max 5000 & classic timing figure 4. external timing parameters (part 3 of 3) asynchronous hold t ime combinatorial logic combinatorial logic max 5000 t ah = ( t in + t ic ) C ( t in + t lad ) + t h t ah = ( t in + t ic ) C ( t in + t lad ) + t h classic clock-to-output delay array clock-to-output delay combinatorial logic max 5000 aco1 in ic od t = t + t + t max 5000 t co1 = t in + t ics + t od t co1 = t in + t ics + t rd + t od t aco1 = t in + t ic + t rd + t od classic classic
978 altera corporation an 78: under standing max 5000 & classic timing examples the following examples show how to use internal timing parameters to calculate the delays for real applications. example 1: first bit of 7483 ttl macrofunction you can analyze the timing delays for macrofunctions that have been subjected to minimization and logic synthesis. a max+plus ii report file that includes the optional equations section lists the synthesized logic equations for the project. these equations are structured so you can quickly determine the logic implementation of any signal. for max 5000 devices, figure 5 shows part of a 7483 ttl macrofunction (a 4-bit full adder). the report file gives the following equations for s1 , the least significant bit of the adder: s1 = output (_lc021 , vcc); _lc02 1 = lcell (_eq026 $ c0); _eq026 = b1 & !a1 # !b1 & a1; figure 5. adder logic t iming for max 5000 architecture the s1 output is the output of macrocell 21 ( _lc021 ), which contains combinatorial logic. the combinatorial logic lcell(_eq026 $ c0) represents the xor of the intermediate equation _eq026 and the carry-in, c0 . in turn, _eq026 is logically equivalent to the xor of inputs b1 and a1 . therefore, the timing delay for s1 in max 5000 devices is as follows: t in + t lad + t comb + t od not not a1 b1 c0 s1 t lad t comb t od t in
altera corporation 979 an 78: under standing max 5000 & classic timing for classic devices, figure 6 shows part of a 7483 ttl macrofunction (a 4-bit full adder). the report file gives the following equations for s1 , the least significant bit of the adder: s 1 = lcell(_eq002); _eq002 = a1 & b1 & c0 # !a1 & b1 & !c0 # a1 & !b1 & !c0 # !a1 & !b1 & c0; figure 6. adder logic t iming for classic architecture the s1 output is the output of the macrocell which contains the combinatorial logic. the _eq002 represents the equation that logically represents the synthesized implementation of a1 , b1 , and c0 . therefore, the timing delay for s1 in classic devices is as follows: t in + t lad + t od example 2: second bit of 7483 ttl macrofunction for complex logic that requires expanders (represented as _x in report files), the expander array delay, t sexp , is added to the delay element. t l a d t o d t i n a 1 c 0 b 1 s 1
980 altera corporation an 78: under standing max 5000 & classic timing for max 5000 devices, the second bit of the 7483 adder macrofunction, s2 , requires shared expanders. the equations are as follows: s2 = _lc019; _lc019 = lcell(_eq023 $ _eq024); _eq023 = _x029 & _x030 & _x031; _x029 = exp(!b1 & !a1); _x030 = exp(!b1 & !c0); _x031 = exp(!a1 & !c0); _eq024 = _x032 & _x033; _x032 = exp(!b2 & a2); _x033 = exp(b2 & a2); figure 7 shows how you can map the logic structure onto the max 5000 architecture with these equations. the timing delay for s2 in max 5000 devices is shown below: t in + t sexp + t lad + t comb + t od figure 7. adder equations mapped to max 5000 architecture t lad t comb t od t in _x029 _x030 _x031 _x032 _x033 c0 a1 b1 a2 b2 t sexp s2 exp exp exp exp exp
altera corporation 981 an 78: under standing max 5000 & classic timing for classic devices, the second bit of the 7483 adder macrofunction, s2 , requires shared expanders. the equations are as follows: s2 = lcell(_eq003); _eq003 = a2 & b1 & b2 & c0 # a1 & a2 & b2 & !_lc017 # !a2 & b1 & !b2 & c0 # a1 & !a2 & !b2 & !_lc017 # !a2 & !b1 & b2 & !_lc018 # !a1 & !a2 & b2 & !c0 # a2 & !b1 & !b2 & !_lc018 # !a1 & a2 & !b2 & !c0; _lc017 = lcell(_eq010); _eq010 = !b1 & !c0; _lc018 = lcell(_eq011); _eq011 = a1 & c0; : figure 8 shows how you can map the logic structure onto the classic architecture with these equations. the timing delay for s2 in classic devices is shown below: t in + t lad + t fd + t lad + t od
982 altera corporation an 78: under standing max 5000 & classic timing figure 8. adder equations mapped to classic architecture example 3: first bit of 7483 ttl macrofunction in low-power mode (classic devices) if a classic device macrocell is set for low-power mode, you must add the low-power adder delay to the total delay through that macrocell. thus, the s1 delay in figure 6 is as follows: t in + t lpa + t lad + t od conclusion the max 5000 and classic device architectures have fixed internal timing delays that are independent of routing. therefore, you can determine the worst-case timing delays for any design before programming a device. total delay paths can be expressed as the sums of internal timing delays. timing models illustrate the internal delay paths for devices and show how these internal timing parameters affect each other. you can use the max+plus ii timing analyzer to automatically calculate delay paths, or hand-calculate delay paths by adding the internal timing parameters for an appropriate timing model. with the ability to predict worst-case timing delays, you can be confident of a designs in-system timing performance. c0 a1 a2 b1 b2 lc017 lc018 t lad t od t in s2 t lad t fd
copyright ? 1995, 1996, 1997, 1998 , 1 9 9 9 altera corporation, 101 innovation drive, san jose, c a 95134, usa, all rights r eserved. by accessing this information, you ag r ee to be bound by the terms of alteras legal notice.

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